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A LOW POWER BIST TPG FOR HIGH FAULT COVERAGE AND HIGH EFFICIENCY

Mayank Chakraverty, Ritaban Chakravarty, Vinay Babu, Kinshuk Gupta

Abstract


This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST. BIST is a device, here part of the functional device is self dedicated to self-testing the correctness of the device.
In general BIST is comprised of two TPGs: LT-RTPG (Low Transition-Random Test Pattern Generator) and 3-Weight WRBIST(Weighted Random Built In Self Test) Minimization of hardware overhead is a major concern of BIST implementation. In test-per-scan BIST, a new test pattern is applied to the inputs of the CUT every m + 1clock cycles, where m is the number of scan elements in the longest scan chain. By using two proposed TPG increasing fault coverage is achieved through the reduction of switching activity, thereby dissipation of power is minimized. Experimental results for ISCAS’89(International Symposium for Circuits and Systems) benchmark circuits shows that the proposed BIST can significantly reduce switching activity during BIST while achieving maximum fault coverage for all ISCAS’89 benchmark circuits. In large circuit, greater reduction in switching activity is achieved. The proposed BIST can be implemented with low area overhead. As seen through experimental results.
Keywords:- BIST,TPG, LT-RTPG and 3-Weight WRBIST, Power Dissipation during test application, Fault Coverage , High Fault efficiency.

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References


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DOI: https://doi.org/10.37628/jvdt.v1i1.29

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