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Analysis of Device Parameters Variation on SRAM Cell for High Performance Memory Design

Farhan Aziz, Vishal Lal Goswami, Ashutosh Dubey, Ranjeet Singh

Abstract


As silicon industry is moving towards the end of the technology roadmap, controlling the variation in device parameters during fabrication is posing a great challenge. The variations in process parameters such as the channel length, width, oxide thickness, dopant-placement in a channel result in a large variation in threshold voltage. This paper investigates the impact of process variation on design metrics of Static Random Access Memory (SRAM) cell, which is used for process-tolerant cache architecture suitable for high-performance memory design. The six-transistor (6T) and seven-transistor (7T) SRAM cells have been used to analyze and evaluate the impact of process variation at 32nm technology. The 7T SRAM bitcell has 60% improvement in SNM at the cost of 11.1% area penalty, 30.7× hold power penalty, 16.7% read delay penalty and 1.2× variability penalty. This shows that the 6T SRAM cell is more robust and consumes less power than the 7T cell. Keywords: hold power, random dopant fluctuation (RDF), line edge roughness (LER), static noise margin (SNM), read access time, static random access memory (SRAM)

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References


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