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Design of High Speed Parallel Prefix Adder Using Triple Carry Operator

M Hemlata, B Lakshmi, R. Jalaja

Abstract


The parallel prefix adder (PPA) performs the addition operation for N-bit simultaneously. PPA enhances the processor's performance in terms of area and speed. Hence, PPA is considered an appropriate adder in the ALU unit of the processor. In this paper, a PPA with a triple carry operator (TCO) is proposed and compared with standard PPAs having the traditional carry operator. In TCO, the generate and propagate signals of N-bits of an adder are combined to obtain the generate and propagate signals of combined bits. The prefix structure in PPA reduces the number of levels to obtain the final carryout and sum. The proposed adder is simulated and synthesized using Xilinx ISE 14.7 and achieves less delay and area compared with the remaining adders

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References


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