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Design CMOS Low Power High Speed Digital 4-Bit Counter at 45 GPDK Technology

Kasaragadda Pravallika, Nagaraju Eduru

Abstract


The low power VLSI circuit is meant to reduce power consumption, chip size, and improve the system'sbattery life and performance. The scaling design, often known as a counter, is used to increase ordecrease the values of an operator based on its prior state. Frequency and time may be monitoredthroughout the counting process. The main issue with scaling circuits is power consumption caused bypower dissipation in the clock while it is in standby mode. The clock signal in a counter consumes onethirdof the total power. The number of switching actions is minimised in this study to decrease power
consumption. The counter's power consumption was reduced even further by decreasing the powerconsumption of the flip-flops. Combining TSPCL with SVL (Self-Controllable Voltage Level) mayaccomplish this. The Flip-Flop operation is performed by TSPCL at a fast speed and low power. TheSVL approach reduces the complexity of the system by suppressing the power generated by leakagecurrent and using fewer transistors. The new design uses 27 percent less energy than the current one.The suggested technique identifies potential applications for low-power contemporary electronics.


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